1. Field of the Invention
This invention relates to a MIS type semiconductor device, and more particularly to the device having source and drain regions formed by self align technique.
2. Description of the Prior Art
Recently, the advancement in microprocessing techniques has enabled the production of the production a MIS (Metal Insulator Semiconductor) transistor having a gate length of 1 micron or less than. In this fine construction MIS transistor, a serious problem is caused in that the effective channel length is shorter than the gate electrode length. It is indispensable to anneal the semiconductor substrate to activate the impurity introduced by the ion implantation. In consequence, the introduced impurity diffuses not only in the longitudinal direction but also in the lateral direction within the semiconductor substrate.
This lateral diffusion of the impurity has influence especially on a P type channel MIS transistor constructed in a CMOS circuit. Source and drain regions of the P type channel MIS transistor are formed generally by ion implantation using boron. The coefficient of diffusion of boron is extremely larger than the coefficient of diffusion of arsenic using the impurity for a N type channel MIS transistor. As a result, the lateral diffusion is conspicuous on the P type channel MIS transistors have been designed. In the case of designing CMOS circuits, the effective channel length of the P type channel MIS transistor was shorter than the N type channel MIS transistor and overlap portions between a gate electrode and source, drain regions of the P type channel MIS transistor grow larger. As these overlap portions grow larger, the parasitic capacity between the gate electrode and the source/drain regions increase to disturb the high speed operation. This may cause the punch through phenomena between source and drain regions to occur. For preventing the decrease of the effective channel length, it is possible to design the gate length somewhat longer, in advance. However, the degree of overlap portions cannot be changed.
FIG. 1 shows a conventional P type channel MIS transistor to solve above mentioned problems. An element isolating insulator layer 11 is formed on a N type silicon substrate 12. A gate electrode 13 is formed on an element forming region through a gate insulator layer 14. Side wall insulator layers 15, 16 are selectively formed on side walls of the gate electrode 13 by the anisotropic dry etching process after depositing the CVD (Chemical Vapor Deposition) insulator layer on the entire surface of the substrate 12.
Source and drain regions 17, 18 are formed by ion implantation of the impurity using the gate electrode 13 and the side wall insulator layer 15, 16 as a mask. Thereafter, a CVD insulator layer 19 covers the entire surface of the substrate 12. Source and drain electrodes 20, 21 are formed through contact holes opening on the CVD insulator layer 19.
Source and drain regions 17, 18 are formed at a distance of the thickness of the side wall insulator layers 15, 16 from edges of the gate electrode 13. Thereafter, edges of the gate electrode 13 and source and drain regions 17, 18 about coincide at diffusion by the annealing. It is able to prevent being too short the effective channel length according to implant the impurity ion on the predetermined position at a distance from the edge of the gate electrode. However, if layer thickness of the side wall insulator layers 15, 16 vary widly, it is feared that edges of source and drain regions 17, 18 are positioned away from the edges of the gate electrode 13, in what is called, an off set gate construction. Even though it is saved from the off set gate construction, there arises a large decrease of the impurity concentration in its distribution along the lateral direction at the channel, source and drain regions, thereby resulting in parasitic resistance.
The parasitic resistance restricts the electric current and lowers the driving ability, at the same time it prevents the high speed operation of the MIS transistor. However, particularly in the P type channel MIS transistor, it is difficult to improve simultaneously the parasitic capacity and the parasitic resistance.
FIG. 2 shows a conventional LDD (Lightly Doped Drain) type MIS transistor to prevent the short channel effect. It is a feature of low concentration impurity regions 22, 23 and high concentration impurity regions 24, 25. Low concentration impurity regions 22, 23 are formed by the ion implantation using a gate electrode 26 as a mask. High density impurity regions 24, 25 are formed by the ion implantation using the gate electrode 26 and side wall insulator layers 27, 28 as a mask.
This LDD type transistor has low concentration impurity regions 22, 23, and therefore prevents the off set gate construction. However, low concentration impurity regions 22, 23, namely, high resistance regions, contact with the source and drain regions, so the electric current through the channel region is restricted.